As ball pitch on integrated circuit packages decrease, it becomes more difficult to fan out signal paths to their appropriate layers. If the pitch becomes small enough, vias cannot fit within the ball grid array (BGA) without violating clearance rules. In the prior art, trace paths are routed outside of the BGA grid before vias are used. This creates parasitic effects on the power and ground connections that can reduce electrical performance of the integrated circuit.
Accordingly, there is a significant need for an apparatus and method that overcomes the deficiencies of the prior art outlined above.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawing have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to each other. Further, where considered appropriate, reference numerals have been repeated among the Figures to indicate corresponding elements.